A phase-locked loop (PLL) is an electronic system that locks in phase and frequency of an output signal to the phase and frequency of an input signal. A PLL is widely used in applications in communication systems and devices, such as FM demodulators, stereo demodulators, tone detectors, frequency synthesizers, etc. A PLL is also commonly employed in digital applications that require a high-frequency periodic signal to synchronize the events between high-performance digital circuits, such as microprocessors, digital signal processors, network processors, synchronous systems, and the like. A PLL is particularly desirable to be integrated with semiconductor integrated circuits (IC) for the various application fields, and implemented by advanced Very-Large-Scale-Integrated-Circuit (VLSI) manufacturing technologies, such as a Complementary Metal-Oxide-Semiconductor (CMOS) manufacturing technology.
As the trend of integrating a complex electronic system on a monolithic semiconductor chip continues, PLLs have become an essential component for nearly all VLSI chips. As an example, a PLL is typically integrated in an advanced digital system, such as a microprocessor to provide synchronized clock signals, among other things. As another example, a PLL is also typically employed in an analog or a mixed-signal chip, such as a high-performance radio frequency (RF) transceiver, to form a frequency synthesizer, which is generally used to modulate a baseband signal in a transmitter and demodulate an incoming RF signal in a receiver. Robust and stable operation is one of the most desirable characteristics of a PLL, determining the overall performance of the circuitry it is integrated with.
While CMOS manufacturing technologies continue scaling down into the deep-submicron and nanometer range, design of PLLs with desirable characteristics is becoming increasingly difficult. One of the many challenges comes from increased sensitivity to on-chip power supply noise due to the reduced supply-to-threshold voltage ratios, which degrades PLL performance, by causing increased phase noise or timing jitter. More specifically, a voltage controlled oscillator (VCO) or a current controlled oscillator (CCO) used in a PLL is particularly sensitive to noise on its power supply. It is essential that the VCO or CCO operates from a “clean” power supply for an advanced PLL architecture.
A supply-regulated PLL architecture is used to provide a clean or regulated supply to the VCO or CCO used in a PLL. As an example, a typical supply-regulated PLL architecture involves using a supply-regulating loop between the loop filter and voltage controlled oscillator (VCO) of a PLL. Such a supply-regulating loop may amplify and buffer the voltage control signal (VCTRL) from the loop filter and generate an adjustable regulated power supply voltage to the VCO (VREG). The main PLL loop operates the VCO at the required frequency by varying VCTRL and hence VREG and the supply-regulating loop keeps VREG independent of variations in the PLL power supply (VDD). The existing supply-regulated PLLs having a configuration described above also typically include a decoupling capacitor between the regulated VCO supply voltage (VREG) and the ground as an effort to eliminate the undesirable AC components in the regulated VCO supply voltage (VREG).
This and other existing supply-regulated PLL structures, however, exhibit a number of apparent problems. First, as the supply-regulating loop itself does not reject VCO power supply noise at frequencies above its bandwidth, the bandwidth of the supply-regulating loop needs to be maximized. This may lead to increased power consumption in the PLL. Second, the use of the VCO decoupling capacitor introduces a higher-order pole which makes compensating the PLL loop difficult. It is desirable to ensure stable PLL operation across a wide range of reference frequencies. For this reason, it is important that the PLL loop dynamics track the reference frequency (ωWREF) while remaining independent of process, voltage and temperature (PVT) variations. In other words, the frequency of any higher order pole should scale with the PLL reference frequency but this is not always the case. Typically, the pole frequency-to-reference frequency ratio varies according to PVT conditions and can also be a function of the multiplication factor of the divide-by-N circuit used in the PLL. Hence, the operational stability of a supply-regulated PLL may be significantly reduced across PVT conditions and PLL usage may be limited to a narrow range of reference frequencies.
In view of these and other problems in the existing supply-regulated PLL structures, there is a need for improved supply-regulated PLL structures and methods of using in order to obtain the desired PLL characteristics while coping with the trend of continuous scaling of VLSI processing technology.